The present invention relates to a semiconductor device and to a method of producing the same. More particularly, the invention relates to technology effective in decreasing the thickness of a package of the surface mount type.
Modern engineering work stations and personal computers require a memory of a small size, yet a sufficiently large capacity to be capable of processing large amounts of data at high speeds. To meet this requirement, technology has been advanced for laminating packages of the surface mount type.
Decreasing the thickness of the individual surface-mount-type packages is essential for the lamination, and various kinds of thin packages have been developed.
For example, Japanese Patent Laid-Open No. 175406/1993 discloses thin packages, such as a TSOP (thin small outline package) and a TSOJ (Thin Small Outline J-lead package) having a semiconductor chip disposed on a chip-mounting portion (a die pad) of a lead frame, a plurality of leads arranged to surround the semiconductor chip, and a resin sealing member for sealing the inner lead portions of the plurality of leads.
There has further been proposed package having a LOC (load on chip) structure, which is one type of the surface-mount-type packages. This package has a structure in which the inner leads are partly arranged on the main surface (element-forming surface) of a semiconductor chip via an insulating tape, the ends of the inner leads are electrically connected to the bonding pads of the semiconductor chip by bonding the wires, and, then, the semiconductor chip, inner lead portions, insulating tape and bonding wires are sealed with a resin. The insulating tape is constituted by a base film of a heat-resistant resin, such as a polyimide, and an adhesive agent applied to both surfaces thereof. A package having an LOC structure of this type has been disclosed in, for example, U.S. Pat. No. 5,234,866.